1. Field of the Invention
The invention relates to semiconductor devices and methods of forming the same and, more specifically, to transistors having a channel region between channel-portion holes and methods of forming the same.
2. Description of the Related Art
Generally, semiconductor devices include discrete elements to place data input by a user in a desired place. The discrete elements include a capacitor for storing data and a transistor for transmitting the data to the capacitor through a line.
The transistor includes a gate pattern disposed on a semiconductor substrate, source and drain regions formed in the semiconductor substrate to overlap the gate pattern, and a channel region disposed in the semiconductor substrate under the gate pattern to transmit user's data. When a voltage is applied to the gate pattern, and the source and drain regions to drive the transistor, the channel region serves as a data transmission route between the source region and the drain region.
However, as a design rule of the semiconductor device is reduced, the channel region and the gate pattern become smaller areas in the transistor. To cope with this change, the channel region is formed by at least one ion implantation process, which is performed in the semiconductor substrate. The channel-portion hole is disposed to extend from a top surface of the semiconductor substrate to a lower region thereof by a predetermined depth, and to contact the channel region. There is provided a gate pattern that fills the channel-portion hole with the trench shape. The gate pattern provides a data transmission route along the semiconductor substrate that defines the channel-portion hole. As such, if a voltage is applied to both the channel-portion hole and the channel region during the operation of the transistor, a body effect is increased due to the channel region around the channel-portion hole, thereby decreasing current driving capability.
On the other hand, U.S. Pat. No. 5,817,558 to Shye Lin Wu et al (the '558 patent) discloses a method of forming a t-gate lightly-doped drain semiconductor device. According to the '558 patent, this method includes forming a pad oxide layer on the semiconductor substrate. A lightly doped layer is formed around the pad oxide layer by implanting impurity ions into the semiconductor substrate, and a first insulating layer is formed on the pad oxide layer. An aperture is formed in the first insulating layer, and a sidewall spacer is formed on the sidewall of the aperture.
The method includes performing an etching process in the semiconductor substrate by using the first insulating layer and the sidewall spacers as an etch mask to form a groove in the substrate. At this time, the sidewall spacers are also removed. A gate oxide layer is formed in and around the groove, and a gate material layer, which fills the aperture and the groove, is formed on the first insulating layer.
Further, the method includes partially performing an etching process in the gate material layer to form a T-shaped gate in the aperture and the groove. Subsequently, the first insulating layer is removed. Heavily doped source and drain layers are formed on the lightly doped layer so that they are arranged at both sides of the T-shaped gate.
However, the method further includes forming an anti-punch-through layer to prevent a contact between the source and the drain in the semiconductor substrate having the groove. The anti-punch-through layer is arranged along the groove to reduce an impurity concentration of the lightly doped layer adjacent to the groove, thereby causing a current leakage while driving the semiconductor device. This is because the lightly doped layer and the anti-punch-through layer have different conductivity types from each other. Furthermore, since the gate oxide layer is partially etched, characteristics of the semiconductor device may be degraded due to the etching damage of the oxide layer.